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RISC-V Processor Model
Barták, Jiří ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.
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Service life increasing of spare part tools for ground cultivation
Černín, Jiří ; Mrňa, Libor (referee) ; Sigmund, Marian (advisor)
This diploma thesis deals with increasing the service life of parts intended for soil cultivation. The work evaluates the current possibilities of increasing the utility value of spare parts. Practical tests will provide recommendations for the most appropriate method to increase durability. The work examines uncharted methods of testing soldered joint. The results are evaluated in terms of quality and economic profitability. All results from this work are based on the basis of practical tests of plowing machine in rocky soil.
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Service life increasing of spare part tools for ground cultivation
Černín, Jiří ; Mrňa, Libor (referee) ; Sigmund, Marian (advisor)
This diploma thesis deals with increasing the service life of parts intended for soil cultivation. The work evaluates the current possibilities of increasing the utility value of spare parts. Practical tests will provide recommendations for the most appropriate method to increase durability. The work examines uncharted methods of testing soldered joint. The results are evaluated in terms of quality and economic profitability. All results from this work are based on the basis of practical tests of plowing machine in rocky soil.
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RISC-V Processor Model
Barták, Jiří ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.
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